With the advancement of semiconductor fabrication processes circuit designs continue to grow in size and complexity. As such, the need for comprehensive verification and validation of a circuit design also increases.
Conventionally, the design of an integrated circuit relied on manual development of directed tests and large regressions to find non-compliances in a circuit design. Test plans consistent with test descriptions were used to write a large number of directed tests. These tests were created using a combination of tools and methodologies created by the engineers working on the design.
Recently, a number of business entities, such as Mentor Graphics of Wilsonville, Oreg. and Cadence Design Systems of San Jose, Calif. have developed and marketed a number of tools and methodologies for use in testing and verifying a design or to test a fabricated circuit to identify non-compliant portions therein.
The tools and methodologies provided by such entities provide functional test capabilities to verify the behavior of the circuit design or the fabricated circuit and can provide other test capabilities that include path delay test (PDT) and transition test (TT). PDT testing can identify faults caused by cumulative propagation delay of a combinational path that increases beyond some specified time duration, and TT testing can identify transition faults gross gate delay such as gates that are slow to rise or slow to fall.
PDT tests are well suited for use to test a representation of a design and for use to test a fabricated version of the design. However, the number of paths in a logic circuit is exponential with the number of lines. So PDT test vector generation can only be performed successfully on a small portion of paths. Accordingly, PDT test coverage for a circuit design and, in turn, a fabricated version of the circuit design is often less than sixty percent. As such, functional tests are executed by automatic test equipment (ATE) to increase the test coverage percentage to above sixty percent. However, functional test generation for an ATE is often time consuming, may or may not be at speed capable, and requires highly specialized pieces of capital equipment.